NAND Gate Glitch — Unequal Delays Cause Sensor Failures

from typing import List, Callable
from dataclasses import dataclass
from io.thecodeforge.logic.models import LogicLevel

@dataclass
class TruthTableRow:
    inputs: List[int]
    output: int

class LogicGate:
    """
    Base class for all logic gate implementations.
    Provides truth table generation and gate simulation.
    """
    
    def __init__(self, name: str, num_inputs: int, func: Callable[[List[int]], int]):
        self.name = name
        self.num_inputs = num_inputs
        self.func = func
    
    def evaluate(self, inputs: List[int]) -> int:
        """
        Evaluate gate output for given binary inputs.
        Validates input count and binary values.
        """
        if len(inputs) != self.num_inputs:
            raise ValueError(
                f"{self.name} expects {self.num_inputs} inputs, got {len(inputs)}"
            )
        for i, val in enumerate(inputs):
            if val not in (0, 1):
                raise ValueError(
                    f"Input {i} must be 0 or 1, got {val}"
                )
        return self.func(inputs)
    
    def truth_table(self) -> List[TruthTableRow]:
        """
        Generate complete truth table for this gate.
        """
        rows = []
        for i in range(2 ** self.num_inputs):
            inputs = [(i >> bit) & 1 for bit in range(self.num_inputs - 1, -1, -1)]
            output = self.evaluate(inputs)
            rows.append(TruthTableRow(inputs=inputs, output=output))
        return rows
    
    def __repr__(self):
        return f"LogicGate({self.name})"


# Define fundamental gates
AND_GATE = LogicGate("AND", 2, lambda inputs: inputs[0] & inputs[1])
OR_GATE = LogicGate("OR", 2, lambda inputs: inputs[0] | inputs[1])
NOT_GATE = LogicGate("NOT", 1, lambda inputs: 1 - inputs[0])
NAND_GATE = LogicGate("NAND", 2, lambda inputs: 1 - (inputs[0] & inputs[1]))
NOR_GATE = LogicGate("NOR", 2, lambda inputs: 1 - (inputs[0] | inputs[1]))
XOR_GATE = LogicGate("XOR", 2, lambda inputs: inputs[0] ^ inputs[1])
XNOR_GATE = LogicGate("XNOR", 2, lambda inputs: 1 - (inputs[0] ^ inputs[1]))


# Print truth table for AND gate
for row in AND_GATE.truth_table():
    print(f"A={row.inputs[0]} B={row.inputs[1]} -> {row.output}")

from io.thecodeforge.logic.gates import (
    AND_GATE, OR_GATE, NOT_GATE,
    NAND_GATE, NOR_GATE, XOR_GATE, XNOR_GATE
)
from io.thecodeforge.logic.display import TruthTableRenderer

def print_all_gate_truth_tables():
    """
    Generate and display truth tables for all seven standard logic gates.
    """
    two_input_gates = [
        AND_GATE, OR_GATE, NAND_GATE,
        NOR_GATE, XOR_GATE, XNOR_GATE
    ]
    
    for gate in two_input_gates:
        print(f"\n{gate.name} Gate Truth Table:")
        print("A | B | Output")
        print("--|---|-------")
        for row in gate.truth_table():
            print(f"{row.inputs[0]} | {row.inputs[1]} |   {row.output}")
    
    print(f"\n{NOT_GATE.name} Gate Truth Table:")
    print("A | Output")
    print("--|-------")
    for row in NOT_GATE.truth_table():
        print(f"{row.inputs[0]} |   {row.output}")


def verify_universality():
    """
    Demonstrate that NAND can implement AND, OR, and NOT.
    """
    # NOT using NAND: tie both inputs together
    def nand_not(a: int) -> int:
        return NAND_GATE.evaluate([a, a])
    
    # AND using NAND: NAND followed by NOT (NAND with tied inputs)
    def nand_and(a: int, b: int) -> int:
        return nand_not(NAND_GATE.evaluate([a, b]))
    
    # OR using NAND: NOT(A) NAND NOT(B)
    def nand_or(a: int, b: int) -> int:
        return NAND_GATE.evaluate([nand_not(a), nand_not(b)])
    
    print("NAND Universality Verification:")
    print("\nNOT from NAND:")
    for a in [0, 1]:
        print(f"  NOT({a}) = {nand_not(a)}")
    
    print("\nAND from NAND:")
    for a in [0, 1]:
        for b in [0, 1]:
            print(f"  {a} AND {b} = {nand_and(a, b)}")
    
    print("\nOR from NAND:")
    for a in [0, 1]:
        for b in [0, 1]:
            print(f"  {a} OR {b} = {nand_or(a, b)}")


print_all_gate_truth_tables()
verify_universality()

from typing import Dict, List, Set
from itertools import product
from io.thecodeforge.logic.simplification import KarnaughMap

class BooleanExpression:
    """
    Represents and simplifies Boolean expressions using
    truth table analysis and algebraic identities.
    """
    
    def __init__(self, variables: List[str], truth_values: Dict[tuple, int]):
        self.variables = variables
        self.truth_values = truth_values
        self.num_vars = len(variables)
    
    def evaluate(self, assignment: Dict[str, int]) -> int:
        """
        Evaluate expression for a given variable assignment.
        """
        key = tuple(assignment[v] for v in self.variables)
        return self.truth_values.get(key, 0)
    
    def minterms(self) -> List[int]:
        """
        Return indices of rows where output is 1.
        Used for sum-of-products canonical form.
        """
        result = []
        for i, (inputs, output) in enumerate(self.truth_values.items()):
            if output == 1:
                minterm_index = 0
                for j, val in enumerate(inputs):
                    minterm_index = minterm_index * 2 + val
                result.append(minterm_index)
        return result
    
    def maxterms(self) -> List[int]:
        """
        Return indices of rows where output is 0.
        Used for product-of-sums canonical form.
        """
        result = []
        for i, (inputs, output) in enumerate(self.truth_values.items()):
            if output == 0:
                maxterm_index = 0
                for j, val in enumerate(inputs):
                    maxterm_index = maxterm_index * 2 + val
                result.append(maxterm_index)
        return result
    
    def simplify(self) -> str:
        """
        Simplify using Quine-McCluskey algorithm.
        Returns minimized Boolean expression.
        """
        from io.thecodeforge.logic.simplification import QuineMcCluskey
        
        minterm_indices = self.minterms()
        if not minterm_indices:
            return "0"
        
        qm = QuineMcCluskey(self.variables)
        prime_implicants = qm.find_prime_implicants(minterm_indices)
        essential = qm.find_essential_implicants(prime_implicants, minterm_indices)
        
        return qm.expression_from_implicants(essential)


# Example: XOR gate expression derivation
xor_truth = {
    (0, 0): 0,
    (0, 1): 1,
    (1, 0): 1,
    (1, 1): 0
}

xor_expr = BooleanExpression(['A', 'B'], xor_truth)
print(f"XOR minterms: {xor_expr.minterms()}")
print(f"XOR simplified: {xor_expr.simplify()}")
# Output: A'B + AB'

from typing import List, Tuple
from io.thecodeforge.logic.gates import AND_GATE, OR_GATE, XOR_GATE, NOT_GATE
from io.thecodeforge.logic.models import Circuit, Wire

class HalfAdder:
    """
    Half adder circuit: adds two single bits.
    Outputs sum (XOR) and carry (AND).
    """
    
    def __init__(self):
        self.name = "Half Adder"
    
    def compute(self, a: int, b: int) -> Tuple[int, int]:
        sum_bit = XOR_GATE.evaluate([a, b])
        carry_bit = AND_GATE.evaluate([a, b])
        return sum_bit, carry_bit


class FullAdder:
    """
    Full adder circuit: adds two bits with carry input.
    Built from two half adders and an OR gate.
    """
    
    def __init__(self):
        self.name = "Full Adder"
        self.half_adder_1 = HalfAdder()
        self.half_adder_2 = HalfAdder()
    
    def compute(self, a: int, b: int, carry_in: int) -> Tuple[int, int]:
        sum_1, carry_1 = self.half_adder_1.compute(a, b)
        sum_out, carry_2 = self.half_adder_2.compute(sum_1, carry_in)
        carry_out = OR_GATE.evaluate([carry_1, carry_2])
        return sum_out, carry_out


class Multiplexer:
    """
    2-to-1 multiplexer: selects one of two inputs based on select line.
    Built from AND, OR, and NOT gates.
    """
    
    def __init__(self):
        self.name = "2:1 MUX"
    
    def compute(self, input_0: int, input_1: int, select: int) -> int:
        not_select = NOT_GATE.evaluate([select])
        and_0 = AND_GATE.evaluate([input_0, not_select])
        and_1 = AND_GATE.evaluate([input_1, select])
        output = OR_GATE.evaluate([and_0, and_1])
        return output


# Demonstrate full adder
adder = FullAdder()
print("Full Adder Truth Table:")
print("A | B | Cin | Sum | Cout")
print("--|---|-----|-----|-----")
for a in [0, 1]:
    for b in [0, 1]:
        for cin in [0, 1]:
            s, cout = adder.compute(a, b, cin)
            print(f"{a} | {b} |  {cin}  |  {s}  |  {cout}")

from dataclasses import dataclass
from typing import List
from io.thecodeforge.logic.models import TimingPath

@dataclass
class GateDelay:
    gate_type: str
    tpd_high_to_low: float  # nanoseconds
    tpd_low_to_high: float  # nanoseconds
    
    @property
    def max_delay(self) -> float:
        return max(self.tpd_high_to_low, self.tpd_low_to_high)


# Typical delays for different logic families
GATE_DELAYS = {
    "TTL_AND": GateDelay("AND", 15.0, 11.0),
    "TTL_OR": GateDelay("OR", 22.0, 15.0),
    "TTL_NOT": GateDelay("NOT", 10.0, 8.0),
    "CMOS_AND": GateDelay("AND", 2.5, 2.0),
    "CMOS_OR": GateDelay("OR", 3.0, 2.5),
    "CMOS_NOT": GateDelay("NOT", 1.5, 1.2),
    "HC_AND": GateDelay("AND", 8.0, 7.0),
    "HC_OR": GateDelay("OR", 9.0, 8.0),
    "HC_NOT": GateDelay("NOT", 6.0, 5.0)
}


class CriticalPathAnalyzer:
    """
    Analyzes timing paths through gate-level circuits
    to identify critical paths and calculate maximum clock frequency.
    """
    
    def __init__(self, gate_delays: dict):
        self.gate_delays = gate_delays
    
    def calculate_path_delay(self, path: List[str]) -> float:
        """
        Calculate total propagation delay through a series of gates.
        """
        total_delay = 0.0
        for gate_name in path:
            if gate_name in self.gate_delays:
                total_delay += self.gate_delays[gate_name].max_delay
            else:
                raise ValueError(f"Unknown gate type: {gate_name}")
        return total_delay
    
    def max_clock_frequency(
        self,
        critical_path: List[str],
        setup_time: float = 2.0,
        clock_to_q: float = 3.0
    ) -> float:
        """
        Calculate maximum clock frequency given critical path.
        f_max = 1 / (t_clk-to-q + t_path + t_setup)
        """
        path_delay = self.calculate_path_delay(critical_path)
        min_period = clock_to_q + path_delay + setup_time
        return 1e9 / min_period  # Convert ns to Hz
    
    def analyze_circuit(self, paths: List[List[str]]) -> dict:
        """
        Analyze all timing paths and identify the critical path.
        """
        results = []
        for i, path in enumerate(paths):
            delay = self.calculate_path_delay(path)
            freq = self.max_clock_frequency(path)
            results.append({
                "path_index": i,
                "gates": path,
                "total_delay_ns": delay,
                "max_frequency_mhz": freq / 1e6
            })
        
        critical = min(results, key=lambda r: r["max_frequency_mhz"])
        return {
            "paths": results,
            "critical_path": critical,
            "max_system_frequency_mhz": critical["max_frequency_mhz"]
        }


# Example: analyze a 4-bit ripple carry adder
cmos_delays = {k: v for k, v in GATE_DELAYS.items() if k.startswith("CMOS")}
analyzer = CriticalPathAnalyzer(cmos_delays)

# Critical path: carry through all 4 full adders
# Each full adder: XOR -> AND -> OR for carry chain
critical_path = ["CMOS_AND", "CMOS_OR"] * 4
result = analyzer.analyze_circuit([critical_path])
print(f"Max frequency: {result['max_system_frequency_mhz']:.1f} MHz")

// io.thecodeforge — cs-fundamentals tutorial

# Quine-McCluskey minimizer for a 3-input majority circuit
# Output is 1 when at least two inputs are HIGH

from itertools import combinations

def minterms_to_binary(minterms: list[int], bits: int) -> set:
    return {f"{m:0{bits}b}" for m in minterms}

def combine(a: str, b: str) -> str:
    diff = sum(1 for i in range(len(a)) if a[i] != b[i])
    if diff == 1:
        return ''.join('-' if a[i] != b[i] else a[i] for i in range(len(a)))
    return None

minterms = [3, 5, 6, 7]  # binary: 011, 101, 110, 111
bits = 3

prime_implicants = set()
current = minterms_to_binary(minterms, bits)

while True:
    next_level = set()
    used = set()
    for a, b in combinations(current, 2):
        combined = combine(a, b)
        if combined:
            next_level.add(combined)
            used.add(a)
            used.add(b)
    prime_implicants.update(current - used)
    if not next_level:
        break
    current = next_level

print("Prime implicants (with - for don't-care):")
for term in sorted(prime_implicants):
    print(f"  {term}")
print("Final expression: AB + AC + BC")

// io.thecodeforge — cs-fundamentals tutorial

# Simulate a static-1 hazard in circuit F = A'C + BC
# When inputs transition from (A,B,C) = (1,0,1) to (1,1,1)
# Signal B arrives later than A' toggle

def gate_delay(signal: float, delay_ns: float) -> float:
    return signal if delay_ns == 0 else None  # simplified

time_ns = 0.0
A, B, C = 1, 0, 1
delay_A_not = 2.0
delay_B = 5.0  # B changes slower

# Before transition
A_not = 0
F_prev = (A_not & C) | (B & C)
print(f"@{time_ns}ns: A={A} B={B} C={C} A'={A_not} F={F_prev}")

# Transition starts: A stays 1, B starts toggling to 1
time_ns = 2.0
A_not = 0  # still old value
B = 0      # hasn't arrived yet
F_current = (A_not & C) | (B & C)
print(f"@{time_ns}ns: A={A} B={B} C={C} A'={A_not} F={F_current}  <-- GLITCH!")

time_ns = 5.0
B = 1
F_current = (A_not & C) | (B & C)
print(f"@{time_ns}ns: A={A} B={B} C={C} A'={A_not} F={F_current}  <-- stable again")

// io.thecodeforge — cs-fundamentals tutorial

class LogicGate:
    def __init__(self, vdd=5.0, gnd=0.0):
        self.vdd = vdd
        self.gnd = gnd
        self.gnd_noise = 0.0  # Oh, the real world

    def and_gate(self, a, b):
        if abs(self.gnd_noise) > 0.3:
            print("Ground bounce: logic undefined")
            return False
        return a > (self.vdd / 2) and b > (self.vdd / 2)

# Simulate dirty ground
gate = LogicGate()
gate.gnd_noise = 0.4
print(gate.and_gate(3.3, 4.8))  # Should be True, but…

// io.thecodeforge — cs-fundamentals tutorial

class Wire:
    def __init__(self, length_mm):
        self.inductance_nh = length_mm * 1.0  # 1 nH/mm rough model
        self.propagation_ns = length_mm * 5.0 / 300.0  # 5 ps/mm

    def signal_fidelity(self, freq_mhz):
        reactance_ohms = 2 * 3.14159 * freq_mhz * self.inductance_nh / 1000
        if reactance_ohms > 50:
            return "Ringing likely—add series termination"
        return "Clean enough for prototype"

wire = Wire(100)  # 10cm wire
print(f"{wire.signal_fidelity(80)}")
print(f"{wire.signal_fidelity(200)}")